Adapting the GACT-X Aligner to Accelerate Minimap2 in an FPGA Cloud Instance

Featured ApplicationFast long-read assembly to reference in AWS cloud FPGA instances.In genomic analysis, long reads are an emerging type of data processed by assembly algorithms to recover the complete genome sample. They are, on average, one or two orders of magnitude longer than short reads from the previous generation, which provides important advantages in information quality. However, longer sequences bring new challenges to computer processing, undermining the performance of assembly algorithms developed for short reads. This issue is amplified by the exponential growth of genetic data generation and by the slowdown of transistor technology progress, illustrated by Moore's Law. Minimap2 is the current state-of-the-art long-read assembler and takes dozens of CPU hours to assemble a human genome with clinical standard coverage. One of its bottlenecks, the alignment stage, has not been successfully accelerated on FPGAs in the literature. GACT-X is an alignment algorithm developed for FPGA implementation, suitable for any size input sequence. In this work, GACT-X was adapted to work as the aligner of Minimap2, and these are integrated and implemented in an FPGA cloud platform. The measurements for accuracy and speed-up are presented for three different datasets in different combinations of numbers of kernels and threads. The integrated solution's performance limitations due to data transfer are also analyzed and discussed.

FPGA Based Light Weight Encryption of Medical Data for IoMT Devices using ASCON Cipher

Internet of Things applications with various sensors in public network are vulnerable to cyber physical attacks. The technology of IoT in smart health monitoring systems popularly known as Internet of Medical Things (IoMT) devices. The rapid growth of remote telemedicine has witnessed in the post COVID era. Data collected over IoMT devices is sensitive and needs security, hence provided by enhancing a light weight encryption module on IoMT device. An authenticated Encryption with Associated Data is employed on the IoMT device to enhance the security to the medical wellness of patient. This paper presents FPGA-based implementation of ASCON-128, a light weight cipher for data encryption. A LUT6 based substitution box (SBOX) is implemented on FPGA as part of cipher permutation block. The proposed architecture takes 1330 number of LUTs, which is 35% less compared to the best existing design. Moreover, the proposed ASCON architecture has improved the throughput by 45% compared to the best existing design. This paper presents the results pertaining to encryption and decryption of medical data as well as normal images. © 2022 IEEE.

Gaming for Better Psychological Health: A Solution Based on the FPGA Zynq 7000

Anxiety and depression are the two most prevalent mental health problems throughout the globe. They may present either suddenly or persistently, with a broad range of symptoms, many of which are often asymptomatic. This need is a direct outcome of the mental illness-related economic and healthcare insurance service burden. The expansion of the COVID-19 pandemic and the resulting increase in the incidence of mental health concerns have both contributed to the rising need for mental health care. In response to these demands, a substantial amount of research is examining alternatives to the usual methods used to treat mental health issues. According to research, digital games include cognitive benefits such as attention management, cognitive flexibility, and information processing. This study dissects and analyses the game 'Space Invaders' in terms of its design and implementation. The game has enormous potential as a resource for the mitigation of some mental health issues in lieu of or in addition to established therapeutic therapies. The resource is inexpensive, readily accessible, globally accessible, beneficial, and not connected with shame. © 2022 IEEE.

The learning must go on: Experience of keeping participants engaged in online robotics competition during COVID-19 lockdown

Participant retention in online learning has often been discussed as a challenge in educational research. During 2020-2021, the existing challenges were burdened by the COVID-19 pandemic. This study explores certain engagement techniques with participants through an online project-based learning mode provided as a part of a nationwide robotics competition during the pandemic. 54 teams (176 participants) from 42 institutions participated in the competition to build a sophisticated Field Programmable Gate Array (FPGA) architecture. The study aims to understand participant engagement, the effect due to COVID-19 pandemic and lockdown, personal development due to competition, and the effect of scaffoldings and guided efforts. Despite the challenges due to the pandemic, additional scaffolding and guided efforts lead to approximately 24% of teams successfully building the architecture. This is similar to an average of 26% in pre-pandemic editions of the competition without these additional scaffolds. These efforts and mode of learning are thus found to successfully engage participants during pandemic. © ISLS.

FAST: FPGA-based Acceleration of Genomic Sequence Trimming

The sheer amount of genomic sequencing data generated daily that requires time-sensitive processing for downstream analysis calls for accelerating the bioinformatics pipelines. Previous studies mainly have attempted accelerating the alignment stage, leaving the other pipeline stages as performance bottlenecks. In this work, we propose the first FPGA-based framework dubbed FAST to accelerate the stages that deal with sequence trimming, in particular adapter and primer removal. FAST supports a comprehensive set of functionalities and is convenient to use by operating on standard genomics data formats. The proposed framework is fully configurable and supports variety of runtime settings. It surpasses the state-of-the-art widely-used adapter trimmer (fastp) by 4.7×-29.4× speed-up, with 10.1×-54.9 less energy, respectively. For clipping primers, which with current existing tool (iVar) accounts for ∼50% of SARS-CoV-2 analysis pipeline, FAST achieves up to 62× speed-up in trimming the virus sequences with a low FPGA resource utilization of 12%. © 2022 IEEE.

Design of epidemic detection system in railway station based on FPGA

Since the outbreak of COVID-19 in 2020, wearing masks and displaying green codes in and out of public places has become a habit. The identity verification of the existing railway station is mainly based on face recognition. Due to the outbreak and persistence of the epidemic, people often need to call out the green code on their mobile phones for staff verification, which takes a lot of time. At the same time, the existing face recognition equipment requires the inbound personnel to take off their masks, which also increases the infection risk of the inbound personnel. In order to reduce the above infection risk and speed up people's entry and exit speed, we have designed a system that can identify people wearing masks and judge whether they are confirmed or suspected cases at the same time. Firstly, the system measures the passenger's body temperature through the infrared temperature measurement module, carries out face detection and recognition at the same time, and queries the recognition results in the database to judge whether the passenger is diagnosed or in close contact. When the passenger is normal, it is allowed to pass, otherwise it is not allowed to pass, and updates the relevant data in the cloud database. The system uses Yolo algorithm as the face detection algorithm, and then carries out face recognition through FaceNet network, so as to judge its identity and query the relevant information of the person in the cloud database. After testing, the iterative loss rate of the system is basically below 0.1 and the accuracy is basically stable above 99%. Considering that we need to use it on embedded devices and the amount of calculation operation of deep learning algorithm is large, and FPGA can well build circuits according to the needs of the model because of its reconfigurability, and FPGA can realize hardware acceleration because it can run in parallel, so we finally choose to deploy the model to FPGA to complete face recognition. © 2022 IEEE.

New Real-Time Impulse Noise Removal Method Applied to Chest X-ray Images.

In this paper, we propose a new Modified Laplacian Vector Median Filter (MLVMF) for real-time denoising complex images corrupted by "salt and pepper" impulsive noise. The method consists of two rounds with three steps each: the first round starts with the identification of pixels that may be contaminated by noise using a Modified Laplacian Filter. Then, corrupted pixels pass a neighborhood-based validation test. Finally, the Vector Median Filter is used to replace noisy pixels. The MLVMF uses a 5 × 5 window to observe the intensity variations around each pixel of the image with a rotation step of π/8 while the classic Laplacian filters often use rotation steps of π/2 or π/4. We see better identification of noise-corrupted pixels thanks to this rotation step refinement. Despite this advantage, a high percentage of the impulsive noise may cause two or more corrupted pixels (with the same intensity) to collide, preventing the identification of noise-corrupted pixels. A second round is then necessary using a second set of filters, still based on the Laplacian operator, but allowing focusing only on the collision phenomenon. To validate our method, MLVMF is firstly tested on standard images, with a noise percentage varying from 3% to 30%. Obtained performances in terms of processing time, as well as image restoration quality through the PSNR (Peak Signal to Noise Ratio) and the NCD (Normalized Color Difference) metrics, are compared to the performances of VMF (Vector Median Filter), VMRHF (Vector Median-Rational Hybrid Filter), and MSMF (Modified Switching Median Filter). A second test is performed on several noisy chest x-ray images used in cardiovascular disease diagnosis as well as COVID-19 diagnosis. The proposed method shows a very good quality of restoration on this type of image, particularly when the percentage of noise is high. The MLVMF provides a high PSNR value of 5.5% and a low NCD value of 18.2%. Finally, an optimized Field-Programmable Gate Array (FPGA) design is proposed to implement the proposed method for real-time processing. The proposed hardware implementation allows an execution time equal to 9 ms per 256 × 256 color image.

A Novel Project-Oriented System on Chip (SoC) Design Course for Computer and Electrical Engineers

This paper describes a novel project-oriented system on chip (SoC) design course. The course is taught in the Computer Science and Engineering (CSE) Department at the University of Texas at Arlington and is offered as CSE 4356 System on Chip Design for computer engineering undergraduates, as CSE 5356 for computer engineering graduate students, and as EE 5315 for electrical engineering graduate students. It is taught as one course combining all numbers. All students are given the same lectures, course materials, assignments, and projects. Grading standards and expectations are the same for all students as well. The course in its current form was first offered in fall 2020 and was taught online due to COVID-19 restrictions. The course was offered again in fall 2021 in a traditional on-campus, in-person mode of delivery. Two seasoned educators, with more than eighty years of total teaching experience, combined to team teach the course. One also brought more than thirty years of industrial design experience to the course. SoC FPGA devices have been available for use by designers for more than 10 years and are widely used in applications that require both an embedded microcomputer and FPGA-based logic for real-time computationally-intense solutions. Such solutions require skills in C programming, HDL programming, bus topologies forming the bridge between FPGA fabric and the microprocessor space, Linux operating systems and virtualization, and kernel device driver development. The breadth of the skills that were conveyed to students necessitated a team teaching approach to leverage the diverse background of the instructors. With such a wide range of topics, one of the biggest challenges was developing a course that was approachable for a greatly varied population of students - a mix of Computer Engineering (CpE) and Electrical Engineering (EE) students at both the graduate and undergraduate level. Another, perhaps less obvious, challenge was the inherently application focus of the course, which presents challenges to many graduate students whose undergraduate degree lacked a robust hands-on design experience. Selection of an appropriate project was key to making the course effective and providing a fun learning experience for students. The projects were aligned to relevant industry applications, stressing complex modern intellectual property (IP) work flows, while still being approachable to students. The design of a universal asynchronous receiver transmitter (UART) IP module in 2020 and a serial peripheral interface (SPI) IP module in 2021 were chosen as the projects for the first two offerings of the course. The Terasic/Intel DE1-SoC development board and Intel Quartus Prime 18.1 design software were the technologies chosen for the course. The development board and basic test instruments were provided to each student in a take-home lab kit. The system on chip design course has proven to be a popular but challenging course for our undergraduate and graduate students in computer engineering and electrical engineering. The course has demonstrated that it is possible to successfully teach an advanced design-oriented course to students of varying majors, levels, educational backgrounds, and cultures. © American Society for Engineering Education, 2022.

Accelerated LD-based selective sweep detection using GPUs and FPGAs

Selective sweep detection carries theoretical significance and has several practical implications, from explaining the adaptive evolution of a species in an environment to understanding the emergence of viruses from animals, such as SARS-CoV-2, and their transmission from human to human. The plethora of available genomic data for population genetic analyses, however, poses various computational challenges to existing methods and tools, leading to prohibitively long analysis times. In this work, we accelerate LD (Linkage Disequilibrium) - based selective sweep detection using GPUs and FPGAs on personal computers and datacenter infrastructures. LD has been previously efficiently accelerated with both GPUs and FPGAs. However, LD alone cannot serve as an indicator of selective sweeps. Here, we complement previous research with dedicated accelerators for the ω statistic, which is a direct indicator of a selective sweep. We evaluate performance of our accelerator solutions for computing the w statistic and for a complete sweep detection method, as implemented by the open-source software OmegaPlus. In comparison with a single CPU core, the FPGA accelerator delivers up to 57.1× and 61.7× faster computation of the ω statistic and the complete sweep detection analysis, respectively. The respective attained speedups by the GPU-accelerated version of OmegaPlus are 2.9× and 12.9×. The GPU-accelerated implementation is available for download here: https://github.com/MrKzn/omegaplus.git. © 2022 IEEE.

Hybrid education in the field of digital technologies

This article is focused on the subject Digital technique, which is lectured at the Faculty of Electrical Engineering of the CTU in Prague. The subject is intended for the students of the 2nd grade of their basic study and each year approx. 70 students participate in this subject. Our aim is to continually increase the quality of laboratory measurements by including up-to-date and modern resources (FPGA development boards and kits) as well as interesting and important achievements in this area in order to make the subject as much interesting and motivating for the students as possible. Unfortunately, the last academic year teaching was negatively influenced by COVID pandemic and by various restrictions it caused, especially unpredictable opening and closures of the university for students, which caused the teaching was mostly performed in the online mode. Due to that, we decided to essentially update and transform the content of the subject towards modern resources and with respect to the above-mentioned principles. The paper contains the description of these updates and upgrades we performed, especially focusing on the updates of laboratory tasks and experiments. The article describes the necessary prerequisites, restrictions and will focus deeper on laboratory tasks. © 2022 IEEE.

FPGA-Based Deep Learning Models for Analysing Corona Using Chest X-Ray Images

Coronavirus is a large family of viruses that affects humans and damages respiratory functions ranging from cold to more serious diseases such as ARDS and SARS. But the most recently discovered virus causes COVID-19. Isolation at home or hospital depends on one's health history and conditions. The prevailing disease that might get instigated due to the existence of the virus might lead to deterioration in health. Therefore, there is a need for early detection of the virus. Recently, many works are found to be observed with the deployment of techniques for the detection based on chest X-rays. In this work, a solution has been proposed that consists of a sample prototype of an AI-based Flask-driven web application framework that predicts the six different diseases including ARDS, bacteria, COVID-19, SARS, Streptococcus, and virus. Here, each category of X-ray images was placed under scrutiny and conducted training and testing using deep learning algorithms such as CNN, ResNet (with and without dropout), VGG16, and AlexNet to detect the status of X-rays. Recent FPGA design tools are compatible with software models in deep learning methods. FPGAs are suitable for deep learning algorithms to make the design as flexible, innovative, and hardware acceleration perspective. High-performance FPGA hardware is advantageous over GPUs. Looking forward, the device can efficiently integrate with the deep learning modules. FPGAs act as a challenging substitute podium where it bridges the gap between the architectures and power-related designs. FPGA is a better option for the implementation of algorithms. The design attains 121μW power and 89 ms delay. This was implemented in the FPGA environment and observed that it attains a reduced number of gate counts and low power. © 2022 Anupama Namburu et al.

VirtLAB: A Low-Cost Platform for Electronics Lab Experiments.

The recent SARS-CoV2 pandemic has put a great challenge on university courses. Electronics teaching requires real laboratory experiences for students, which cannot be realized if access to physical infrastructures is prohibited. A possible solution would be to distribute to students, at home, electronics equipment suitable for laboratory experiments, but no reasonable product is currently available off-the-shelf. In this paper, the design and development of a very-low-cost experimental board tailored to these needs is presented. It contains both programmable prototyping circuitry based on a microcontroller and an FPGA and a set of measurement instruments, similar to the ones found on a typical lab desk, such as a digital storage oscilloscope, multimeter, analog signal generator, logic state analyzer and digital pattern generator. A first board, suitable for analog and digital electronics experiments, has been designed and manufactured, and is described in this paper. The board has been successfully used in master's degrees and PhD courses.

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis

Field programmable gate arrays (FPGAs) have become widely prevalent in recent years as a great alternative to application-specific integrated circuits (ASIC) and as a potentially cheap alternative to expensive graphics processing units (GPUs). Introduced as a prototyping solution for ASIC, FPGAs are now widely popular in applications such as artificial intelligence (AI) and machine learning (ML) models that require processing data rapidly. As a relatively low-cost option to GPUs, FPGAs have the advantage of being reprogrammed to be used in almost any data-driven application. In this work, we propose an easily scalable and cost-effective cluster-based co-processing system using FPGAs for ML and AI applications that is easily reconfigured to the requirements of each user application. The aim is to introduce a clustering system of FPGA boards to improve the efficiency of the training component of machine learning algorithms. Our proposed configuration provides an opportunity to utilise relatively inexpensive FPGA development boards to produce a cluster without expert knowledge in VHDL, Verilog, or the system designs related to FPGA development. Consisting of two parts–a computer-based host application to control the cluster and an FPGA cluster connected through a high-speed Ethernet switch, allows the users to customise and adapt the system without much effort. The methods proposed in this paper provide the ability to utilise any FPGA board with an Ethernet port to be used as a part of the cluster and unboundedly scaled. To demonstrate the effectiveness of the proposed work, a two-part experiment to demonstrate the flexibility and portability of the proposed work–a homogeneous and heterogeneous cluster, was conducted with results compared against a desktop computer and combinations of FPGAs in two clusters. Data sets ranging from 60,000 to 14 million, including stroke prediction and covid-19, were used in conducting the experiments. Results suggest that the proposed system in this work performs close to 70% faster than a traditional computer with similar accuracy rates. © 2022 Informa UK Limited, trading as Taylor & Francis Group.

Remote Prototyping of FPGA-Based Devices in the IoT Concept during the COVID-19 Pandemic

This paper presents a system for the remote design and testing of electronic circuits and devices with FPGAs during COVID-19 and similar lockdown periods when physical access to laboratories is not permitted. The system is based on the application of the IoT concept, in which the final device is a test board with an FPGA chip. The system allows for remote visual inspection of the board and the devices linked to it in the laboratory. The system was developed for remote learning taking place during the lockdown periods at Poznan University of Technology (PUT) in Poland. The functionality of the system is confirmed by two demonstration tasks (the use of the temperature and humidity DHT11 sensor and the design of a generator of sinusoidal waveforms) for students in the fundamentals of digital design and synthesis courses. The proposed solution allows, in part, to bypass the time-consuming simulations, and accelerate the process of prototyping digital circuits by remotely accessing the infrastructure of the microelectronics laboratory.

Applying Lightweight Elliptic Curve Cryptography ECC and Advanced IoT Network Topologies to Optimize COVID-19 Sanitary Passport Platforms Based on Constrained Application Protocol

Being in a period of covid-19 urges us to develop platforms that help in minimizing the spread of the virus. Thus, this paper proposes a Medical IoT platform that is created to control citizens’ access to public areas. Our platform focuses on three scenarios on which a citizen is admitted to: being vaccinated which means that the person holds a vaccine pass that contains a unique QR code, possessing a PCR test which means that the person holds a unique barcode, and having an RFID tag which contains a unique identifier. All scenarios start with the same test which allows us to detect the presence of a citizen using a PIR IoT Client node, and end with one last test which is the face recognition to verify the present citizen is indeed who he/she claims to be. Only if one of the scenarios is valid can the citizen be allowed to access the public space. To ensure communication between the IoT nodes we developed our platform based on the Constrained Application Protocol CoAP. As for the security of the payloads, we have implemented RSA, AES, and ECC encryption algorithms to protect the integrity of the data and prevent any attacks. We also based our platform on 4 types of network topologies namely star, tree, mesh, and cluster. The use of different topologies and different encryption methods will allow us to eventually choose which one best matches the platform’s requirements, and that is in terms of execution time and memory occupation. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.

Optimized implementation of an improved KNN classification algorithm using intel FPGA platform: Covid-19 case study

The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to solve this drawback. However, using traditional hardware description language (HDL) to implement FPGA-based accelerators requires a high design time. Fortunately, the open computing language (OpenCL) high level parallel programming tool allows rapid and effective design on FPGA-based hardware accelerators. In this study, OpenCL has been used to examine speeding up the DCT-KNN algorithm on the FPGA parallel computing platform through applying numerous parallelization and optimization techniques. The optimized approach of the improved KNN could be used in various engineering problems that require a high speed of classification process. Classification of the COVID-19 disease is the case study used to examine this work. The experimental results show that implementing the DCT-KNN algorithm on the FPGA platform (Intel De5a-net Arria-10 device was used) gives an extremely high performance when compared to the traditional single-core-CPU based implementation. The execution time for our optimized design on the FPGA accelerator is 44 times faster than the conventional design implemented on the regular CPU-based computational platform.

A CASE STUDY ON MIGRATING THE LAB ACTIVITIES ONLINE – STUDENTS’ PROFESSORS’ PERSPECTIVES

The laboratory activities for an undergraduate course on digital design are normally developed around a physical platform. After the COVID19 prevention measures were established the activities had to move online, thus, the professors had to find some rapid solutions to preserve the initial goals of the laboratory. This article discusses the goals of such laboratory (in relation to the broad engineering domain), how are these goals fulfilled by a physical platform and what was the online solution that was developed to overcome the challenges. Furthermore, the opinions of students that were attending the both types of activities (physical and online) are presented. © 2021, National Defence University - Carol I Printing House. All rights reserved.

Teaching Computer System Courses with an Online Large-Scale Method

Domain-Specific Architectures (DSAs) and hardware-software co-design are greatly emphasized in the CS community, which demands a significant number of participants with Computer System (CSys) capabilities and skills. Conventional CSys courses in a lecture-lab format are limited in physical resources and inherently difficult to cultivate talents at a large scale. Online teaching is a potential alternative to instantly enlarge the face-to-face class size. Unfortunately, simply putting the lecture contents in CSys courses online lacks 1) personal attention, 2) learner-instructor interactions, and 3) real-hardware experimental environments. To tackle the above challenges, we introduce a four phase online CSys course program and the related teaching methods for a cloud-based teaching platform. The four-phase course program included two basic/required stages and two advanced/optional stages to promote students' knowledge and skill level with appropriate personal attention. We studied if online interaction methods, such as in-class chat and one-on-one online grading interview, can strengthen the connections between teachers and students in both lectures and labs. We created a heterogeneous cloud platform to enable students nationwide to reliably conduct labs or projects on remote programmable hardware. We believe that our proposed course design methodology is beneficial to other CScourses in the post-COVID-19-era. © 2021 IEEE.

Remote Versus In-hand Hardware Laboratory in Digital Circuits Courses

The COVID-19 pandemic has isolated many engineering students at home and complicated access to instrumentation and hardware resources necessary to support laboratory courses. One viable alternative to bringing the hardware to students (and the correspondingly high overhead associated with shipping laboratory kits all over the world) is to enable remote access to that hardware. A remote lab allows students to access real hardware physically located in a single location from anywhere in the world. Advances in cloud computing allow students to take advantage of a full-fledged remote experience without compromising what they could have accomplished if they were physically present in the lab. While remote access laboratories are not new, the COVID-19 pandemic has enabled a unique opportunity to compare learning with how remote access to real hardware vs. hands-on access to the same hardware. Comparisons between the two modes of learning were made for a junior level course in digital circuit design using field programmable gate array (FPGA) hardware offered via remote access in autumn 2020 and via hands-on access in the same course in winter 2020. Detailed assessments of student work were grounded in Bloom's Taxonomy to classify the complexity of student cognition and learning. This study presents assessment results associated with a single laboratory assignment that was the first in a series of laboratory assignments in the digital design course. Work from 41 students from each offering were analyzed within the first five levels of Bloom's Taxonomy. Results show that students performed significantly better in terms of overall scores and analyze skills when presented with remote access to laboratory hardware than when having that hardware in hand. Comparisons between the two settings in the remaining four levels of Bloom's Taxonomy (remember, understand, apply, evaluate) were not significantly different between the two offerings. These results complement other studies that highlight the benefits of remote laboratories. Accordingly, the increased efficiency and cost savings of the remote lab approach can offer stable and reliable instruction well beyond the COVID-19 crisis. © American Society for Engineering Education, 2021

Design and Implementation of Smart Healthcare Monitoring System Using FPGA

With growing health awareness and the increasing cost of medical care, there is an impetus to new and advanced technologies for disease prevention and early diagnosis and treatment. The weakest link exposed by the COVID-19 pandemic in India is health care. Investment in critical health Infrastructure aided by modern technology is the need of the hour. So, this project aims to develop a comprehensive healthcare monitoring system by blending IoT and VLSI. It can monitor a patient’s basic health signs as well as the room condition where the patients are now in real time. We use Nexys4 Artix7 as a processor. In this system, six sensors are used to capture the data from the hospital environment named heartbeat sensor, body, and room temperature sensor, fall detection sensor, blood pressure sensor, air quality monitoring sensors, ECG sensor. The condition of the patients is conveyed via the ThingSpeak website and telephonic calls/SMS to relatives, medical staff. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.